1. Field of the Invention
The present invention relates to a voltage level converter circuit for converting the level of an input voltage.
2. Description of the Background Art
A flash memory must have a voltage of various levels applied to the memory cell. For example, in a DINOR type flash memory, various levels of voltages as shown in the following Table 1 must be applied corresponding to each operation mode.
In Table 1, the voltage to the left of the slash (/) sign indicates the level of the voltage applied in a selected state. The voltage to the right of the slash sign indicates the level of the voltage to be applied in a nonselected state.
A voltage level converter circuit for converting the voltage level is required to supply a voltage of different levels.
FIG. 29 is a circuit diagram showing a structure of a conventional voltage level converter circuit. Referring to FIG. 29, the voltage level converter circuit includes P channel MOS transistors P1 and P2, N channel MOS transistors N1 and N2, an inverter I1, a power supply voltage node nVcc, and nodes nVIN, nVN, n1 and n2.
The operation of this voltage level converter circuit will be described hereinafter.
When voltage Vin supplied to node nVIN attains a high (H) level (logical high : 3.3V), P channel MOS transistor P1 is turned on and P channel MOS transistor P2 is turned off. This causes node n1 to be pulled up to the level of power supply voltage Vcc (here, 3.3V), whereby N channel MOS transistor N2 is turned on. In response, node n2 attains the level of voltage VNN that is supplied to node nVN (here, 11V), whereby N channel MOS transistor N1 is turned off.
When voltage Vin attains a low (L) level (logical low: 0V), P channel MOS transistor P1 is turned off and P channel MOS transistor P2 is turned on. This causes node n2 to be driven to the level of power supply voltage Vcc (here, 3.3V), whereby N channel MOS transistor N1 is turned on. In response, node n1 attains the level of voltage VNN (here, xe2x88x9211V) supplied to node nVN, whereby N channel MOS transistor N2 is turned off.
The above-described operation can be summarized as in the following Table 2.
A circuit that can set voltage Vout output from node n1 to the level of power supply voltage Vcc (3.3V) or voltage VNN (xe2x88x9211V) depending upon the H/L of voltage Vin supplied to node nVIN is called a voltage level converter circuit.
A circuit that converts the voltage level by switching cross-coupled N channel MOS transistors N1 and N2 as shown in FIG. 29 is called a CVSL (Cascade Voltage Switch Logic).
However, usage of this CVSL causes a high voltage across the source and drain of N channel MOS transistors N1 and N2. Hot electrons will be generated to deteriorate the switching operation. There was a problem that the reliability of the transistor is degraded.
For example, in the conventional voltage level converter circuit of FIG. 29, a voltage of 14.3V is applied across the source and drain of N channel MOS transistor N1 that is OFF when voltage Vin attains an H level.
An object of the present invention is to provide a voltage level converter circuit that insures reliability of a transistor by alleviating the voltage applied on each transistor forming the voltage level converter circuit.
According to an aspect of the present invention, a voltage level converter circuit includes an output node, a first node having a first voltage according to an input voltage, a first transistor connected between the first node and the output node, and turned on when the input voltage attains a first logic level, a second node having a second voltage, a second transistor connected between the second node and the output node, and turned on when the input voltage attains a second logic level, and a third transistor of a first conductivity type connected between the output node and the second transistor, and having a gate to which a first control signal is supplied according to the level of a second voltage.
According to another aspect of the present invention, a voltage level converter circuit includes an output node, a first node having a first voltage, a first transistor of a first conductivity type connected between the output node and the first node, and turned on when an input voltage attaining a first logic level is supplied to its gate, a second node having a second voltage, a second transistor of the first conductivity type connected between the output node and the second node, and turned on when the input voltage attains a second logic level, a third transistor of the first conductivity type connected between the gate of the second transistor and the second node, a fourth transistor of the first conductivity type connected between the gate of the third transistor and the second node, and having a gate connected to the gate of the second transistor, a fifth transistor of the first conductivity type connected between the gate of the first transistor and a drain of the fourth transistor, and having a gate supplied with a control signal according to the level of a second voltage, a sixth transistor of a second conductivity type connected between the gate of the fifth transistor and the gate of the third transistor, and having a gate connected to the gate of the second transistor, and a seventh transistor of the second conductivity type connected between the gate of the fifth transistor and the gate of the fourth transistor, and having a gate connected to the gate of the third transistor.
According to a further aspect of the present invention, a level converter circuit includes a first node having a first voltage, a first output node, a first voltage converter circuit connected between the first node and the first output node, responsive to an input first switch signal for supplying a first internal voltage according to the first voltage to the first output node, a second node having a second voltage, a second output node, a second voltage converter circuit connected between the second node and the second output node, and responsive to an input second switch signal for supplying a second internal voltage according to the second voltage to the second output node, a first transistor of a first conductivity type connected between the first node and the second output node, and having a gate connected to the first output node, and a second transistor of the first conductivity type connected between the second node and the second output node.
An advantage of the present invention is that the voltage across the source and drain of a second transistor can be alleviated to improve the reliability of the operation of the second transistor.
Another advantage of the present invention is that a first voltage can be accurately provided from an output node.
A further advantage of the present invention is that the first and second nodes can be completely disconnected.